SGX – Technology & Policy

On the recent side-channel attacks on Intel SGX – Technology & Policy

2017-03-01T12:00:00Z

Side-channel attacks are my favorite attack in computer security because they poke giant holes in the abstraction and security models that system designers are using. When I hear of a new attack avenue in this space, my first reaction often is “wow, that is so cool” and “I didn’t even think about that.”

In the past week, two papers have been published on arXiv detailing side-channel attacks on Intel SGX. While the existence of such attacks should be taken seriously by people designing systems using Intel SGX (which includes yours truly), these particular attacks are not very interesting.

First of all, these attacks really shouldn’t come as a surprise to anyone following this space. Cache-based side-channel attacks are a well-known attack vector. Many papers detailing new techniques have been published over the last couple of years. There’s Evict+Time and Prime+Probe, Flush+Reload, Flush+Flush, etc. Ge et. al. present a good overview of the current state of the art. Intel explicitly states in their Enclave Writer’s Guide that they don’t protect against attacks at cache line or higher granularity.

Second of all, both attacks are exploiting well-known flaws in modular exponentiation implementations. We know how to do constant-time RSA. On top of that, both papers are at best slightly misleading in describing their attack targets.

From the first paper:

As our victim enclave we chose an RSA implementation from the Intel IIP crypto library in the Intel SGX SDK. The attacked decryption variant is a fixed-size sliding window exponentiation, the code is available online at [32]. The Intel IIP library includes also a variant of RSA that is hardened against cache attacks [33].

If you look at how these two variants are used, you can see that only computations with the public exponent are done with the “vulnerable” variant, whereas computations with the private exponent use the “hardened” variant. So, unless you are somehow swapping your public and private exponents, using this crypto library as documented will prevent this attack for you.

From the second paper’s abstract:

We perform a Prime+Probe cache side-channel attack on a co-located SGX enclave running an up-to-date RSA implementation that uses a constant-time multiplication primitive.

Even though the library they use might have a multiplication primitive that is constant-time, as the authors explain further on in the paper, the modular exponentiation primitive is not. In fact, the modular exponentiation algorithm is the textbook example of an algorithm with a secret-dependent branch:

int modexp(int base, int exponent, int modulus) {
    int result = 1;
    for (int i = 0; i < exponent.bits(); i++) {
        result = modsqr(result, modulus);
        if (exponent & (1<<i)) { // access bit `i`
            result = modmul(result, base, modulus);
        }
    }
    return result;
}

If for each iteration of the loop you can detect whether the multiplication happenned or not, you can reconstruct the individual bits of the exponent. This is a fun attack, but as mentioned, this is basically the most well-known timing attack, first described by Kocher 22 years ago. Oh and the library? It implements the blinding mitigation also mentioned in that seminal paper.

To summarize: Yes, programs running with Intel SGX are vulnerable to side-channel attacks. The same side-channel attacks that have been used for years on modern x86 platforms. This is well-documented. SGX does present a slightly different threat model which makes deployment of side-channel attacks more likely. Hopefully everyone using SGX is implementing countermeasures. They do exist, and are already implemented by most cryptography libraries.

Intel has full control over SGX – Technology & Policy

2015-10-13T12:00:00Z

Intel has full control over what software you can run in SGX. This might seem redundant: Intel makes the processor, so of course they have full control. Yet the truth is slightly more inconvenient. When Intel processors don’t run the instructions in your standard software (whether incorrectly or at all), that is a defect at best and a breach of contract at worst. Yet the SGX instruction set includes in its specification that Intel has the authority to make this go/no-go decision.

Let’s take a closer look at how exactly this is specified, since it is pretty well-hidden. After creating and measuring a secure enclave using ECREATE, EADD, and EEXTEND, the EINIT instruction needs to be executed before execution control can be transferred to the enclave. The EINIT instruction has 2 inputs: SIGSTRUCT and EINITTOKEN. SIGSTRUCT contains information about the enclave including an expected hash of the memory. As the name implies, SIGSTRUCT is also cryptographically signed using some key. EINITTOKEN also contains information about the enclave including the same expected hash of the memory as well as the expected public key for the signature. EINITTOKEN must be MACed using the so-called launch key. Both SIGSTRUCT and EINITTOKEN are checked by EINIT and must be valid for execution to proceed succesfully.

Since the launch key is a symmetric cryptography device, surely this key is not widely distributed and most likely is CPU-specific. But how can one obtain this key? The EGETKEY instruction can be used to obtain SGX keys, including the launch key. But this is a user-mode instruction that can only be executed from inside an enclave. There seems to be a chicken-and-egg problem here: to launch an enclave, we need the launch key. To get the launch key, we need to launch an enclave! Here’s the catch: the EINITTOKEN need not be valid if SIGSTRUCT is signed by an Intel key that is baked into the processor.

Thus, Intel can distribute an Intel-signed “launch enclave” that is able to hand out correctly-MACed EINITTOKENs that can then be used to start other enclaves. But they can include whatever logic they want in the launch enclave so Intel can at its sole discretion choose not to MAC a particular EINITTOKEN.

As most things SGX, this “feature” is severely underdocumented. The terms “launch key” and “launch enclave” are only mentioned a few times in the SGX programming reference and never in the whitepapers or tutorials. At the time of writing, nowhere else on the Internet is there any mention of these keywords, except for one insightful Quora answer that I wish I had read months ago.

What reason could Intel have for this architecture? Along with the fact that SGX is being disabled by default, this looks like Intel is again just setting this security technology up for failure due to the lack of widespread adoption by developers and users alike (cf. TXT, SMX, TPM).

SGX Hardware: A first look – Technology & Policy

2015-10-08T12:00:00Z

Without much fanfare, Intel has released Software Guard Extensions (SGX) in Skylake. When I say “without much fanfare,” I mean practically only the following paragraph hidden on page 3 of a press fact sheet:

BETTER SECURITY. The Skylake architecture has been designed to enable better security, including Intel® Software Guard Extensions (Intel® SGX) that can provide an additional level of hardware-based protection by putting data into a secure container on the platform, and Intel® Memory Protection Extensions (Intel® MPX) that can help prevent buffer flow attacks. [What’s a buffer flow attack? Ed.] To be fully utilized, Intel SGX and Intel MPX require additional software capabilities, which will begin to be delivered by the ecosystem later this year.

It has been extremely difficult to find actual hardware that supports SGX. BIOS support is required–the BIOS needs to set aside memory for the Enclave Page Cache (EPC)–but of course no vendor will mention anything about this on their website, nor will they (be able to) answer when you inquire regarding this specific issue.

To my delight, by using Google to search past week results for “intel sgx” for the last few months, I was finally able to find a driver download site that linked this Dell driver. According to Dell’s website, this driver is compatible with the following machine models:

Inspiron 11 i3153
Inspiron 11 i3158
Inspiron 13 i7353
Inspiron 13 i7359
Inspiron 15 i7568

At first I couldn’t find these models mentioned anywhere, but a few days later the i7359 showed up at NewEgg and then at Frys. So, I drove to Sunnyvale (where Frys had the i7359-2435SLV in stock) and I can now confirm that SGX is real:

It’s interesting to note that SGX was disabled in the BIOS by default, so most consumers will not be able to benefit from this feature at all.

The maximum size of the EPC on this laptop is 128MB. This means that enclaves requiring more memory than that will need regular paging between the EPC and main memory. It’s not clear whether such a copy would require re-encryption of the page, the EPC itself is already encrypted so it might not be necessary.

The laptop comes with Windows 10 which runs excruciatingly slow–not surprising considering it only has 4GB of RAM. I installed Arch Linux on it because it’s one of the few distro’s that has an installer with a very recent kernel (4.2.2), required for such new hardware.

I collected some CPUID and MSR information to see what SGX features are supported:

CPUID

                         bit 2 (SGX) is set
                         v
 7h(0h) 00000000h 029c67afh 00000000h 00000000h

     Max. enclave size 2^31 bytes (32-bit mode)
  Max. enclave size 2^36 bytes (64-bit mode) |
    No extended SSA features supported    |  |
SGX version 1 supported  |                |\/|
               v         v                vvvv
12h(0h) 00000001h 00000000h 00000000h 0000241fh

              all enclave attributes supported
              |\       all XSAVE bits supported
              vv                  vv
12h(1h) 00000036h 00000000h 0000001fh 00000000h

   EPC physical address 80200000h
        ////|     |\\\\\\\  EPC size 93.5 MiB
        vvvvv     vvvvvvvv  vvvvv     vvvvvvvv
12h(2h) 80200001h 00000000h 05d80001h 00000000h

MSR

                bit 18 (SGX_ENABLE) is set
                |   bit 0 (LOCK) is set
                v   v
3ah 00000000_00040005h (IA32_FEATURE_CONTROL)

I’m currently writing a simple Linux kernel driver to be able to actually use SGX. I managed to generate a Page Fault using the ENCLS[EBLOCK] instruction, so at least something seems to be working.

I really wish Intel would be more forthcoming with information about and developer support for SGX. The hardly-announced release and default-disabled BIOS setting don’t warrant much hope for the future of SGX.

In the mean time, I intend to write more blog posts in the near future as I try to get SGX up and running. Here’s a cliff hanger for you: the Dell driver package mentioned earlier contains a file aesm_service.exe that contains the string “SGX EPID provisioning network failure.” I’ll try to tell you more about it next time.

Update 2015-12-09: Please see my sgx-utils repository for any open-source SGX utilities, including a bare-bones development Linux driver.